The nomenclature for microchip manufacturing left reality a couple generations ago. Intel’s 14A process is not a true 14A half-pitch. It’s kind of like how they started naming CPUs off “performance equivalents” instead of using raw clock speed. And this isn’t just Intel. TSMC, Samsung, everyone is doing half-pitch equivalent naming now a days.This is the industry roadmap from 2022: <a href="https:&#x2F;&#x2F;irds.ieee.org&#x2F;images&#x2F;files&#x2F;pdf&#x2F;2022&#x2F;2022IRDS_Litho.pdf" rel="nofollow">https:&#x2F;&#x2F;irds.ieee.org&#x2F;images&#x2F;files&#x2F;pdf&#x2F;2022&#x2F;2022IRDS_Litho.p...</a>
If you look at page 6 there is a nice table that kind of explains it.Certain feature sizes have hit a point of diminishing returns, so they are finding new ways to increase performance. Each generation is better than the last but we have moved beyond simple shrinkage.Comparing Intel’s 14A label to TSMCs 16A is meaningless without performance benchmarks. They are both just marketing terms. Like the Intel&#x2F;AMD CPU wars. You can’t say one is better because the label says it’s faster. There’s so much other stuff to consider.

Do you know the name of the company that produces the EUV machine? is it ASML?It is my understanding that only ASML had cracked the EUV litography, but if there&#x27;s another company out there, that would be an interesting development to watch.

Intel says a lot of things but until they put them out in the field I don&#x27;t believe a word they say

Intel has a 1.4nm process in the pipeline for ~2027. They just took delivery on their first high NA EUV machine in order to start working on it.Their gamble however is that they need to figure out DSA, a long storied technology that uses self-forming polymers to allow less light to sharply etch smaller features.If they figure out DSA, they will likely be ahead of TSMC. If not, it will just be more very expensive languishing.

Well, &quot;extreme UV&quot; these days. 13.5nm, larger than the &quot;feature size&quot;. And even that required heroic effort in development of light sources and optics.

Its so hard to even fathom 200+ Million Transistors in 1 square millimeter !And, to think, it&#x27;s all done with light !We live in interesting times !

Translating 197 M&#x2F;mm2 into the dimensions of a square, we get a dimension of 71nm. If we compute the &quot;half-pitch&quot;, that&#x27;s 35.5nm.230 M&#x2F;mm2 translates to 33nm &quot;half-pitch&quot;.Of course, transistors aren&#x27;t square and aren&#x27;t so densely packed, but these numbers are more real IMO.

200 million transistors per square millimeter.Gallons per mile only makes sense when you are talking about dragsters.

What’s the argument for either? They are, of course, equivalent… might as well pick the one where bigger=better.

Stupid beginner question: is MTr&#x2F;mm² really the right thing to be looking at? Shouldn&#x27;t it be more like mm²&#x2F;MTr ? This feels kind of like these weird &quot;miles per gallon&quot; units, when &quot;gallons per mile&quot; is much more useful...

Yes, generally one of the trends has been movement toward specialized coprocessors&#x2F;accelerators. This was happening before the recent AI push and has picked up steam.If you think of an SOC, the chip in your phone, more and more of the real estate is being dedicated to specialized compute (AI accelerators, GPUs, etc. vs general purpose compute (CPU).At the enterprise scale, one of the big arguments NVIDIA has been making, beyond their value in the AI market, has been the value of moving massive, resource intense workloads from CPU to more specialized GPU acceleration. In return for the investment to move their workload, customers can get a massive increase in performance per watt&#x2F;dollar.There are some other factors at play in that example, and it may not always be true that the transistors&#x2F;mm^2 is always lower, but I think it illustrates the overall point.

The design optimization software for modern semiconductors is arguably the most advanced design software on earth with likely tens if not hundreds of millions of man-years put into it. It takes into account not only the complex physics that apply at the nano-scale but also the interplay of the various manufacturing steps and optimizes trillions of features. Every process change brings about new potential optimizations, so rather than compensating for bigger nodes it actually widens the gap further. By analogy, the jump from hatchet to scalpel in the hands a layman is far less than the jump from hatchet to scalpel for a skilled surgeon.

In general, yes, but all the chip design companies have already invested a whole lot of time and engineering resources into squeezing as much as possible from each transistor. But those kinds of optimizations are certainly part of why we sometimes see new CPU generations released on the same node.

Everyone generally does that before sending the design to the fab.Not to say that improvements and doing more with less are impossible, they probably aren&#x27;t, but it&#x27;s going to require significant per design human effort to do that.

Such optimisation would apply equally to the more dense processes, though.

Some yeah, but many of these optimizations aren&#x27;t across-the-board performance improvements, but rather specializations that favor specific kinds of workloads.There are the really obvious ones like on-board GPUs and AI accelerators, but even within the CPU you have optimizations that apply to specific kinds of workloads like specialized instructions for video encode&#x2F;decode.The main &quot;issue&quot;, such as it is, is that this setup advantages vertically integrated players - the ones who can release software quickly to use these optimizations, or even going as far as to build specific new features on top of these optimizations.For more open platforms you have a chicken-and-egg problem. Chip designers have little incentive to dedicate valuable and finite transistors to specialized computations if the software market in general hasn&#x27;t shown an interest. Even after these optimizations&#x2F;specialized hardware have been released, software makers often are slow in adopting them, resulting in consumers not seeing the benefit for a long time.See for example the many years it took for Microsoft to even accelerate the rendering of Windows&#x27; core UI with the GPU.

Not understanding chip design - but is it possible to get more computational bang with less transistors - are there some optimizations to be had? Better design that could compensate for bigger nodes?

BSPDN is not about putting devices on the front and back, the logic layer is still mostly 2D, it&#x27;s about the power connects moving to the back of the chip so there&#x27;s less interference with logic and larger wiring can be used.

&gt; This 1.6nm process will put them around 230 MTr&#x2F;mm2Would it be that x2 (for front &amp; back)?E.g., 230 on front side and another 230 on back side = 460 MTr&#x2F;mm2 TOTAL

I&#x27;d say they haven&#x27;t been very competitive with AMD in performance per watt&#x2F;dollar in the ryzen era, specifically due to process advantage. (On CPU dies especially, with less advantage for AMDs I&#x2F;O dies.) I&#x27;d agree they have done a good job advancing other aspects of their designs to close the gap, though.

Are intel really just the best chip designers on the earth or why can they compete with such densities with AMD?

Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr&#x2F;mm2 wile Samsung is at 150 MTr&#x2F;mm2 and Intel is at 123 MTr&#x2F;mm2. This 1.6nm process will put them around 230 MTr&#x2F;mm2 by 2026. When viewed by this metric, Intel is really falling behind.

&gt;The metric means what it has always meantThat&#x27;s just patently wrong.The measurement used to refer to feature size [0]. It used to be a physical measurement of a thing in nanometers hence nmNow it&#x27;s a free for all marketing team names it whatever the fuck they want. That&#x27;s why you get stuff like intel 10nm being equivalent to AMD 7nm. [1]. It&#x27;s not real.&gt;Who cares?You...else we wouldn&#x27;t be having this discussion[0] <a href="https:&#x2F;&#x2F;en.wikipedia.org&#x2F;wiki&#x2F;Semiconductor_device_fabrication#Feature_size" rel="nofollow">https:&#x2F;&#x2F;en.wikipedia.org&#x2F;wiki&#x2F;Semiconductor_device_fabricati...</a>[1] <a href="https:&#x2F;&#x2F;www.pcgamer.com&#x2F;chipmaking-process-node-naming-lmc-paper&#x2F;" rel="nofollow">https:&#x2F;&#x2F;www.pcgamer.com&#x2F;chipmaking-process-node-naming-lmc-p...</a>

what is a rough rule of thumb for each 1nm reduction? What does that increase in transistor density look like each year? If the jump is bigger (5nm-&gt;3nm), does that rate of change increase too?trying to understand the economic impact of these announcements as I don&#x27;t understand this topic well enough

The metric means what it has always meant: lower numbers mean higher transistor density on some area (the digital part) of the chip.What more do you want? It’s as meaningful as a single number ever could be.If you’re a consumer - if you don’t design chips - lower number means there’s some improvement somewhere. That’s all you need to know. It’s like horse powers on a car. The number doesn’t tell you everything about the performance under all conditions but it gives a rough idea comparatively speaking.If you’re a chip designer then you never cared about the number they used in naming the process anyway. You would dig into the specification and design rules from the fab to understand the process. The “nm” number might show up in the design rules somewhere.. but that’s never been relevant to anyone, ever.I really don’t understand why so many commenters feel the need to point out that “nm” doesn’t refer to a physical dimension. Who cares? It doesn’t have any impact on anyone. It’s very mildly interesting at best. It’s a near meaningless comment.

Nope that&#x27;s what it meant a long time ago. Nowadays, the nm number represents the smallest possible element on the chip, typically the gate length, which is smaller than the size of a transistor.This means that when different manufacturers use a different transistor design, their &#x27;nm&#x27; process could be the same but their transistor density different.

They&#x27;re using the wrong units if we need to consider the nanometer as something other than a measure of distance.

Wouldn&#x27;t 2nm have 4x the density of 4nm?

Dimensions go by 1&#x2F;root(2) to double density...so about .7 per generation.

Number represents transistor density. 2nm has ~twice the density of 4nm. If you ignore nm as unit of distance it makes sense.

1.6 nm is 16 A. If they continue the BS for much longer, the &quot;feature size&quot; will be smaller than the lattice of Si.

TSMC N5 is indeed about 30% more Transistors&#x2F;mm2 than N7 as you might expect so seems reasonably meaningful?

Because it lost meaning somewhere between a micron and 100nm.From roughly the 1960s through the end of the 1990s, the number meant printed gate lengths or half-pitch (which were identical).At some point, companies started using &quot;equivalences&quot; which became increasingly detached from reality. If my 50nm node had better performance than your 30nm node because I have FinFETs or SOI or whatever, shouldn&#x27;t I call mine 30nm? But at that point, if you have something less than 30nm somewhere in your process, shouldn&#x27;t you call it 20nm? And so the numbers detached from reality.So now when you see a 1.6nm process, it&#x27;s think &quot;1.6nm class&quot;, rather than that corresponding to any specific feature size, and furthermore, understand that companies invent class number exaggerations differently. For example, an Intel 10nm roughly corresponds to Samsung &#x2F; TSMC 7nm (and all would probably be around 15-30nm before equivalences).That should give you enough for a web search if you want all the dirty details.

It’s not meaningless, it’s near meaningless. That’s what the nm stands for, right?

Because it&#x27;s not measuring anything, except the tech generation. It conveys about as much information as &quot;iPhone 14&quot;.

It stopped being an actual measure of size long ago. The nm is t Nanometer anything it’s just a vague marketing thing attempting some sort of measure of generations

process&#x2F;node &quot;size&quot; has, for some time now, been divorced from any actual physical feature on or of the chip&#x2F;transistor itself. See the second paragraph of: <a href="https:&#x2F;&#x2F;en.wikipedia.org&#x2F;wiki&#x2F;2_nm_process" rel="nofollow">https:&#x2F;&#x2F;en.wikipedia.org&#x2F;wiki&#x2F;2_nm_process</a> for additional details

Wonder how long until its back to round numbers? - 800pm

&gt;1.6nmGotta love how we now have fractions of a near meaningless metric.

While you are correct that it is Intel trying to catch TSMC, you are wrong about the origin of backside power delivery. The idea originated at Intel sometime ago, but it would be very ironic if TSMC implements it before Intel...

OP never said Intel wasn&#x27;t trying to catch up. As far as backside power delivery, this is literally what Intel has been working on. It is called PowerVia.<a href="https:&#x2F;&#x2F;www.intel.com&#x2F;content&#x2F;www&#x2F;us&#x2F;en&#x2F;newsroom&#x2F;news&#x2F;powervia-test-shows-industry-leading-performance.html" rel="nofollow">https:&#x2F;&#x2F;www.intel.com&#x2F;content&#x2F;www&#x2F;us&#x2F;en&#x2F;newsroom&#x2F;news&#x2F;powerv...</a>

Except for backside power. Intel published and had a timeline to ship at least one generation ahead of TSMC. I haven’t been tracking what happened since, but Intel was ahead on this one process improvement. And it’s not a small one, but it doesn’t cancel out their other missteps. Not by half.

This isn&#x27;t a comparison of shipping processes though, it&#x27;s just roadmap products. And in fact until this announcement Intel was &quot;ahead&quot; of TSMC on the 2026 roadmap.

Intel is the one trying to catch up to TSMC, not vice versa!The link you give doesn&#x27;t have any details of Intel&#x27;s 18A process, including no indication of it innovating in any way, as opposed to TSMC with their &quot;backside power delivery&quot; which is going to be critical for power-hungry SOTA AI chips.

Fabs have a 3+ year lead time from prototyping the node to having it produce production wafers.

This will also come in 2026, so not that far ahead.

This is a response to something that’s coming in 2 years? Incredible how far ahead they are

Sounds like a response to Intel&#x27;s 18A process [0], which is also coming in 2026.[0] <a href="https:&#x2F;&#x2F;www.tomshardware.com&#x2F;tech-industry&#x2F;manufacturing&#x2F;intel-18a-based-cpus-will-ramp-to-high-volume-in-2026" rel="nofollow">https:&#x2F;&#x2F;www.tomshardware.com&#x2F;tech-industry&#x2F;manufacturing&#x2F;int...</a>

It seems the actually impressive thing here is the 15-20% less power consumption at same n2 complexity&#x2F;speed.

The &quot;Hollywood accounting&quot; transistor density aside, I think a new metric needs to become mainstream: &quot;wafers per machine per day&quot; and &quot;machines per year manufactured&quot;.Getting these machines built and online is more important than what one machine (that might be less than 6 per year) can do.The information, I&#x27;m sure, is buried in their papers, but I want to know what node processes are in products available now.

There&#x27;s still the question though of why they didn&#x27;t do this decades ago - seems very obvious that this layout is better. What changed that made it possible only now and not earlier?

&gt; You need very tiny wires through very tiny holes in locations very precisely aligned on both sides. Aligning things on the scale of nanometers is very, very hard.Do you need to align that precisely? Can&#x27;t the power side have very large landing pads for the wires from the signal side to make it much easier?

Thanks this was a very useful summary for me!

so the wafer is a huge ground plane? still can&#x27;t see how one side is separate from the other if its the same block.

thank you for the explanation! It really helped

ELI5:ICs are manufactured on silicon disks called wafers. Discs have two sides, and traditionally, everything was done on top. We can now do power on the bottom. This makes things go faster and use less power:* Power wires are big (and can be a bit crude). The bigger the better. Signal wires are small and precise. Smaller is generally better.* Big wires, if near signal wires, can interfere with them working optimally (called &quot;capacitance&quot;).* Capacitance can slow down signals on the fine signal wires.* Capacitance also increases power usage when ones become zeros and vice-versa on signal wires.* Big wires also take up a lot of space.* Putting them on the back of the wafer means that things can go faster and use less power, since you don&#x27;t have big power wires near your fine signal wires.* Putting them in back leaves a lot more space for things in front.* Capacitance between power wires (which don&#x27;t carry signal) actually helps deliver cleaner power too, which is a free bonus!This is hard to do, since it means somehow routing power through the wafer. That&#x27;s why we didn&#x27;t do this before. You need very tiny wires through very tiny holes in locations very precisely aligned on both sides. Aligning things on the scale of nanometers is very, very hard.How did I do?

How many power layers are there? Or how do the power &quot;wires&quot; cross over each other?Are they sparse, like wires? Or solid, like the ground plane of a PCB? Are there &quot;burried vias&quot;?

Signal wires and power wires are not routed together, but separately.As a result, transistors are sandwiched between two wiring stacks. Resulting in lower noise, but makes heat removal a bit harder AFAICS.See the image at: <a href="https:&#x2F;&#x2F;www.custompc.com&#x2F;wp-content&#x2F;sites&#x2F;custompc&#x2F;2023&#x2F;06&#x2F;Intel-PowerVia-backside-power-delivery-03.jpg" rel="nofollow">https:&#x2F;&#x2F;www.custompc.com&#x2F;wp-content&#x2F;sites&#x2F;custompc&#x2F;2023&#x2F;06&#x2F;I...</a>

<a href="https:&#x2F;&#x2F;www.imec-int.com&#x2F;en&#x2F;articles&#x2F;how-power-chips-backside" rel="nofollow">https:&#x2F;&#x2F;www.imec-int.com&#x2F;en&#x2F;articles&#x2F;how-power-chips-backsid...</a> has some explanation that&#x27;s a bit beyond ELI5, but they have 2 pictures:frontside: <a href="https:&#x2F;&#x2F;www.imec-int.com&#x2F;_next&#x2F;image?url=%2Fsites%2Fdefault%2Ffiles%2F2022-11%2Fimec%2520-%2520Figure%25201%2520-%2520Frontside%2520power%2520delivery.png&amp;w=1280&amp;q=75" rel="nofollow">https:&#x2F;&#x2F;www.imec-int.com&#x2F;_next&#x2F;image?url=%2Fsites%2Fdefault%...</a>backside: <a href="https:&#x2F;&#x2F;www.imec-int.com&#x2F;_next&#x2F;image?url=%2Fsites%2Fdefault%2Ffiles%2F2022-11%2Fimec%2520-%2520Figure%25202%2520-%2520Backside%2520power%2520delivery%2520-%2520concept.png&amp;w=1280&amp;q=75" rel="nofollow">https:&#x2F;&#x2F;www.imec-int.com&#x2F;_next&#x2F;image?url=%2Fsites%2Fdefault%...</a>Another graphic samsung used: <a href="https:&#x2F;&#x2F;www.thelec.net&#x2F;news&#x2F;photo&#x2F;202210&#x2F;4238_4577_1152.jpg" rel="nofollow">https:&#x2F;&#x2F;www.thelec.net&#x2F;news&#x2F;photo&#x2F;202210&#x2F;4238_4577_1152.jpg</a>From <a href="https:&#x2F;&#x2F;www.tomshardware.com&#x2F;pc-components&#x2F;cpus&#x2F;samsung-to-introduce-backside-power-delivery-to-2nm-class-production-node-report" rel="nofollow">https:&#x2F;&#x2F;www.tomshardware.com&#x2F;pc-components&#x2F;cpus&#x2F;samsung-to-i...</a>&gt; Typically, backside power delivery enables thicker, lower-resistance wires, which can deliver more power to enable higher performance and save power. Samsung&#x27;s paper noted a 9.2% reduction in wiring length, enhancing performance

instead of signals and power path going through the same side (frontside) causing all sorts of issues and inefficiency, they&#x27;re decoupling where power is coming from (from the other, backside, err side).More importantly, intel saw it as one of two key technologies of them moving into angstrom era, and was touting itself they&#x27;ll be the first one to bring it to life (not sure they did).. so this seems to be more of a business power move.more on all of it from anandtech: <a href="https:&#x2F;&#x2F;www.anandtech.com&#x2F;show&#x2F;18894&#x2F;intel-details-powervia-tech-backside-power-on-schedule-for-2024" rel="nofollow">https:&#x2F;&#x2F;www.anandtech.com&#x2F;show&#x2F;18894&#x2F;intel-details-powervia-...</a>

Not ELI5 but I found this 20mn video pretty informative <a href="https:&#x2F;&#x2F;www.youtube.com&#x2F;watch?v=hyZlQY2xmWQ" rel="nofollow">https:&#x2F;&#x2F;www.youtube.com&#x2F;watch?v=hyZlQY2xmWQ</a>

I&#x27;m also clueless. First search brings up <a href="https:&#x2F;&#x2F;www.tomshardware.com&#x2F;news&#x2F;intel-details-powervia-backside-power-delivery-network" rel="nofollow">https:&#x2F;&#x2F;www.tomshardware.com&#x2F;news&#x2F;intel-details-powervia-bac...</a> with a nice diagramIt looks like the topology for backside moves the transistors to the middle so &quot;singal wires and power wires are decoupled and optimized separately&quot; instead of &quot;compete[ing] for the same resources at every metal layer&quot;

So, if I understood that correctly, &quot;frontside&quot; actually is the top side, and &quot;backside&quot; is actually the bottom side. They&#x27;re delivering power from the bottom (substrate) side, and connecting the data on the top side.

An article on the topic though about Intel:<a href="https:&#x2F;&#x2F;spectrum.ieee.org&#x2F;backside-power-delivery" rel="nofollow">https:&#x2F;&#x2F;spectrum.ieee.org&#x2F;backside-power-delivery</a>

there is a good youtube video that explains it <a href="https:&#x2F;&#x2F;www.youtube.com&#x2F;watch?v=hyZlQY2xmWQ" rel="nofollow">https:&#x2F;&#x2F;www.youtube.com&#x2F;watch?v=hyZlQY2xmWQ</a>

This isn&#x27;t quite right. Big wires (ideally entire planes) deliver power. Small wires deliver signal. Half and half isn&#x27;t the right split, and you don&#x27;t want to make power wires smaller.The very different requirements of the two is where a lot of the gains come in.

Half your wires deliver power, half deliver signal. So if you do both on the same side, you need twice the density of wires. If you split the delivery into two parts, you get double the density without needing to make things smaller.

could someone ELi5 the backside power delivery please ?

Here&#x27;s a very good youtube video on the subject of backside power delivery I watched a few days ago. <a href="https:&#x2F;&#x2F;youtu.be&#x2F;hyZlQY2xmWQ?si=JuXtzRy0U0onEzoe" rel="nofollow">https:&#x2F;&#x2F;youtu.be&#x2F;hyZlQY2xmWQ?si=JuXtzRy0U0onEzoe</a>

I am not sure I understand backside in this instance and 
the illustration in the article didn&#x27;t entirely help.In general, at least in older time, one side of the CPU has all 
the nice pins on it, and the motherboard has a pincushion that the pins match nicely. 
At the top of the CPU you put a HUGE heatsink on it and off you go.In this configuration the power delivery must be via the pincushion,
through some of the pins.Intuitively that sounds to me like the power is coming in the backside?
But given that it is a big deal I am missing something.Is the power fed from the &quot;top&quot; of the cpu where the heatsink would sit?

Intel has made lots of big promises, they have yet to catch us to TSMC

Sounds like an easy short for you then.

There are definitely going to be people taking a bet on the Intel foundry, but Intel has tried this before and it has worked badly.

Intel hasn&#x27;t got a great track record in recent history. Really hoping they can hit their timeline though.

A16 in 2027 vs Intel&#x27;s 18A in full swing by 2026 feels like a miss on TMSCs behalf. This looks like an open door for fabless companies to try Intel&#x27;s foundry service.

if people find the topic interesting, I recommend the book &quot;Chip War&quot; [1]It&#x27;s a great read. very dense in narrative facts.[1] <a href="https:&#x2F;&#x2F;www.amazon.com.au&#x2F;gp&#x2F;aw&#x2F;d&#x2F;1398504122&#x2F;ref=ox_sc_act_image_2?smid=ANEGB3WVEVKZB&amp;psc=1" rel="nofollow">https:&#x2F;&#x2F;www.amazon.com.au&#x2F;gp&#x2F;aw&#x2F;d&#x2F;1398504122&#x2F;ref=ox_sc_act_i...</a>

Available in Apple products this Christmas, everybody else&#x27;s in the back half of the decade, maybe.

I love that they&#x27;re using the back side now. It reminds me of finally using the back of a PCB.

So much for physical limitations, it seems you can keep halving smaller till infinity.

The needs of AI&#x2F;HPC at the chip level weren&#x27;t clear to me. Thanks for the insightful answer.

I imagine it&#x27;s because AI and HPC processors are typically utilized much more fully than your regular desktop processor.A typical desktop CPU is designed to execute very varied and branch-heavy code. As such they have a lot of cache and a lot of logic transistors sitting idle at any given time, either waiting for memory or because the code is adding not multiplying for example. You can see that in the die shots like this[1] for example. I imagine the caches are relatively regular and uniform and as such as less complex signal wiring, and idle transistors means lower power requirements.AI and HPC processors are more stream-oriented, and as such contain relatively small cachees and a lot of highly-utilized logic transistors. Compare the desktop CPU with the NVIDIA A100[2] for example. Thus you got both complex wiring, all those execution units needs to be able to very quickly access the register file, and due to the stream-oriented nature one can fully utilize most of the chip so a more complex power delivery network is required.edit: Power delivery tracks can affect signal tracks due to parasitic coupling if they&#x27;re close enough, potentially causing signals to be misinterpreted by the recipient if power usage fluctuates which it will do during normal operation (if say an execution unit goes from being idle to working on an instruction, or vice versa). Thus it can be challenging to fit both power and signal tracks in close proximity.[1]: <a href="https:&#x2F;&#x2F;wccftech.com&#x2F;amd-ryzen-5000-zen-3-vermeer-undressed-high-res-die-shots-close-ups-pictured-detailed&#x2F;" rel="nofollow">https:&#x2F;&#x2F;wccftech.com&#x2F;amd-ryzen-5000-zen-3-vermeer-undressed-...</a>[2]: <a href="https:&#x2F;&#x2F;www.tomshardware.com&#x2F;news&#x2F;nvidia-ampere-A100-gpu-7nm" rel="nofollow">https:&#x2F;&#x2F;www.tomshardware.com&#x2F;news&#x2F;nvidia-ampere-A100-gpu-7nm</a>

There are certain trade offs when designing process. TSMC researched with partners how AI and HPC (high performance computing) chips most likely will look like and adjusted process accordingly.In fact this is big deal as until recently the processes were more tailored toward mobile application (that is were trading some switching performance for lower power consumption). Look like we are back in 2000s when speed&#x2F;density is again more important than power consumption.

As opposed to low power processors (e.g laptops&#x2F;phones), that tend to have less complex wiring and less dense power delivery networks

&gt; This technology is tailored specifically for AI and HPC processors that tend to have both complex signal wiring and dense power delivery networksUh?

TSMC unveils 1.6nm process technology with backside power delivery