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JEDEC Extends DDR5 Memory Spec to 8800 MT/S, Adds Anti-Rowhammer Features

zdw | 139 points

https://stefan.t8k2.com/rh/PRAC/index.html

  Chapter 16: "DDR5 Per Row Activation Counting (PRAC)". PRAC introduces two key mechanisms for comprehensive Rowhammer defenses: an Activation Counter for every DRAM row and a mechanism that triggers when an Activation Counter reaches a specific threshold. This allows the DRAM to pause the memory controller from issuing new commands, giving it time to refresh potential victim rows. In the words of a DRAM industry veteran who will remain nameless, PRAC is the biggest change to DRAM in decades. Thus, I thought I should write up a brief article summarizing the change and its potential to solve Rowhammer once and for all.

transpute | 11 days ago

I'd like to see the spec tackle latency with a "send then confirm" approach.

Ie. The RAM can reply to a read request with data, then a couple of clock cycles later it can confirm (via a flag) that the data it originally sent was correct.

This is helpful because it means the timing can be tightened to the typical access times, rather than the worst case access time (eg. the slowest preamp on the highest capacitance memory row/column).

Things like CPU's already have provisions for handling not-yet-confirmed information, and can roll back state if delivered info turns out to be wrong.

Yes, it adds complexity to the whole system, but it seems worth it for a -30% change to memory latency.

londons_explore | 11 days ago

> Unfortunately, the laws of physics driving DRAM cells have not improved much over the last couple of years (or decades, for that matter), so memory chips still must operate with similar absolute latencies, driving up the relative CAS latency. In this case 14ns remains the gold standard, with CAS latencies at the new speeds being set to hold absolute latencies around that mark.

Some gaming memory kits can do 10ns or less latency. Though I guess if memory latency is your bottleneck, you should look at HBM.

theandrewbailey | 11 days ago

The article doesn't mention much about chip-to-controller distance or path length, presumably this suffers from the same issues we currently see where low power devices (and in some desktop configurations as well) can't really ever get those speeds unless the DRAM chips are near or on top of the CPU substrate.

It's nearly impossible to do those numbers in modern mobile form factors, even CAMM is having a hard time getting there with modularised memory.

oneplane | 11 days ago

I'm always a fan of bigger numbers, but I wish more time/money/whatever was put into letting DDR5 run at those XMP/EXPO speeds when using 4 DIMMs.

AzzyHN | 11 days ago

I'm a bit confused, DDR5 products are already out - as are CPUs and motherboards that support them.

How can this change happen retroactively? Would motherboard manufacturers just need to update the BIOS to enable new XMP configurations? (For when this new, higher transfer rate RAM becomes available)

Night_Thastus | 11 days ago

Please make ECC mandatory.

snvzz | 11 days ago

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SEXMCNIGGA38578 | 11 days ago

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SEXMCNIGGA5068 | 11 days ago

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SEXMCNIGGA6864 | 11 days ago

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